Phase-locked loop (PLL) integrated circuits are frequently used to generate clock signals for synchronous integrated circuit systems. As will be understood by those skilled in the art, PLL integrated circuits may multiply a reference clock frequency by some number to thereby generate a relatively high frequency clock. This multiplying number can be a fractional number if fractional dividers are utilized in a feedback loop of the PLL. One typical technique to implement a fractional divider is to utilize a multi-modulus divider (MMD) with a delta-sigma modulator (DSM), which outputs a sequence of integer numbers having a fractional average value. The MMD uses these integer numbers as divisors. For example, these integer numbers can be any one of [N1, N2], where N1 and N2 are determined by the desired fractional number and the DSM order. To achieve proper operation, there should be no delays or intermediate divisors of the MMD. One example of fractional divider is disclosed in commonly assigned U.S. Pat. No. 8,559,587 entitled “Fractional-N Dividers Having Divider Modulation Circuits Therein with Segmented Accumulators,” the disclosure of which is hereby incorporated herein by reference.
An example of a programmable MMD with extended range is disclosed in an article by Cicero S. Vaucher et al., entitled “A Family of Low-Power Truly Modular Programmable Dividers in Standard 0.35-um CMOS Technology,” IEEE JSSC, Vol. 35, No. 7, July 2000. A shown by FIGS. 1-2, a portion of this MMD 100 includes several stages of div2/3 cells 110 and logic circuits (e.g., OR gates, inverters). Each div2/3 cell includes four (4) level-sensitive D-type latches and three (3) AND gates, connected as illustrated. When signal MODin=1 and signal P=1, a divide-by-3 function is realized so that the states 201, 202 change as follows: (0,1)→(1,1)→(0,1). In addition, when signal MODin=0 and signal P=X (i.e., X=0 or 1), a divide-by-2 function is realized so that the states 201, 202 of corresponding D-type latches change as follows: (0,1)→(1,1)→(0,1). Thus, when node 201 is logic 1, MODout repeats the value of MODin and when node 201 is logic 0, MODout is logic 0, with the latch states changing at negative edges of signal Fin. As shown by FIG. 1, each stage of div2/3 cells samples its own MODin and generates its own MODout, with the rightmost input MODin being set high to a logic “1” value. Based on this configuration, each MODout signal is a positive pulse with the pulse width being one period of its own Fin. During this period, each stage has one chance to perform a “check”, when its MODin is high, to determine whether it is supposed to function as a divide-by-3 cell or a divide-by-2 cell depending on its input P. The period of Fout (i.e., Tout) is related to the period of Fin (i.e., Tin) as follows:Tout=Tin(P<0>+P<1>21+ . . . +P<n−1>2n−1+P<n>2n),which means the divisor is equivalent to the binary number P<n:0> (2≦P<n:0>≦2n+1−1). Unfortunately, one problem with the MMD of FIGS. 1-2 is that when a new P<n:0> is loaded, the divisor does not directly change to the new divisor, but can get an uncertain intermediate value before becoming the new value. This property of the MMD of FIGS. 1-2 is not acceptable for fractional divider applications where any discrepancy will result in an error division ratio. U.S. Pat. No. 6,760,397 to Wu et al. and U.S. Pat. No. 6,501,816 to Kouznetsov et al. also disclose efforts to develop multi-modulus dividers for programmable frequency divider and fractional-N divider applications.
Still further conventional dividers may use cascaded chains of cells that divide by two or three as a function of a modulus control bit (MC) (e.g., ÷2 for MC=0, ÷3 for MC=1). Thus, a cascade of N cells can take any divide ratio from 2N to 2N+1−1 as a function of MC1 through MCN. Unfortunately, the duty cycle of the output divided frequency is typically less than 50%, which is a requirement for many frequency generating circuits for timing applications. A typical solution to achieve the 50% duty cycle requirement is to terminate the frequency divider chain by a divide-by-two flip-flop, which is triggered only by rising (or falling) edges at its input. As will be understood by those skilled in the art, the output of the flip-flop is high for one period of the incoming signal and low for the next period, such that the duty cycle is always 50%. But, with this solution, the output divide ratios can only take even values (e.g., 4, 6, 8, 10 . . . ). An attempt to correct this limitation by providing multi-modulus dividers that support 50% duty cycle output signals is disclosed in an article by Yu-Che Yang et al., entitled “A Dual-Mode Truly Modular Programmable Fractional Divider Based on a 1/1.5 Divider Cell,” IEEE Microwave and Wireless Components Letters, Vol. 15, No. 11, pp. 754-756, November (2005).
Still further examples of frequency dividers that support 50% duty cycle generation are disclosed in U.S. application Ser. No. 14/136,012, filed Dec. 20, 2013, entitled “Half-Integer Frequency Dividers That Support 50% Duty Cycle Signal Generation,” and U.S. application Ser. No. 14/013,599, filed Aug. 29, 2013, entitled “Self-Adaptive Multi-Modulus Dividers Containing DIV2/3 Cells Therein,” the disclosures of which are hereby incorporated herein by reference. Examples of fractional divider circuits are disclosed in U.S. application Ser. No. 14/573,146, filed Dec. 17, 2014, entitled “Fractional Divider Based Phase Locked Loops with Digital Noise Cancellation,” and U.S. application Ser. No. 14/575,212, filed Dec. 18, 2014, entitled “Self-Calibrating Fractional Divider Circuits,” the disclosures of which are hereby incorporated herein by reference.